Currently, circuits are designed using any number of programming tools including high-level modeling languages such as SystemC. These tools enable a design engineer to design, test, and verify circuits prior to manufacturing the circuit. These tools may include a simulator allowing the design engineer to simulate a performance of the designed circuit and programmed via the SystemC classes and macros. However, in current implementations simulation runtime can become extended and dominated by idle cycles when clock-sensitive processes are executed on each clock edge or event but do not change a model state.